Difference between revisions of "Milestones"
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====PHASE 1==== | ====PHASE 1==== | ||
* Define common multi-core events | * Define common multi-core events | ||
− | * Port | + | * Port Scalasca distributed trace file analysis to cluster environment |
− | * Develop additional | + | * Develop additional Scalasca patterns for hardware counter profile data |
* '''Automate use of TAU call-path profiles for selective EPILOG tracing''' | * '''Automate use of TAU call-path profiles for selective EPILOG tracing''' | ||
Revision as of 20:12, 14 July 2009
Goals that emphasize interaction between institutions are marked in bold.
Contents
UO
PHASE 1
- Add routine-level and message passing AI
- Develop experimentation framework and user frontend
- Develop comparative analysis modules
- Update PerfDMF for regression analysis
- OTF format updates for EPILOG
- Evaluate sample-based and direct measurement integration
PHASE 2
- Develop controller for parametric experiments
- Develop user-interface for ACA power tool
- Build PRA prototype, link with software test harness
- Implement joint measurement support
- Update PerfDMF for PerfSuite data
- Incorporate PAPI features for multi-core
PHASE 3
- Port AI on HPC systems and test
- Complete AE framework and release
- Integrate ACA with experimentation system
- Complete ACA framework and release
- Integrate PRA with application groups
- Merge automatic profile analysis with KOJAK
UTK
PHASE 1
- Define common multi-core events
- Port Scalasca distributed trace file analysis to cluster environment
- Develop additional Scalasca patterns for hardware counter profile data
- Automate use of TAU call-path profiles for selective EPILOG tracing
PHASE 2
- Implement additional PAPI network components
- Test distributed trace file analysis on production applications
- Migrate contextual hardware counter information to PAPI standard
- Incorporate PerfSuite and TAU profiles into EXPERT analysis
PHASE 3
- Continue to develop and deploy component PAPI
- Incorporate events from PAPI components into KOJAK analysis
- Extend distributed trace analysis to more parallel paradigms
- Integrate low-overhead statistical hardware counter profiling with TAU and PerfSuite
NCSA
PHASE 1
- Update core library for current processors/OS
- Incorporate Perfmon2 in hardware counter library
- Develop user-oriented reference manual
- Java API design and development (XML access)
- Begin integration with PerfDMF
- Install project software suite at NCSA
- PerfSuite v1.0
PHASE 2
- Update core library for current processors/OS
- Java XML API developed and released
- Java hardware counter API underway
- Develop engineering guide
- Integrate PerfDMF access with PerfSuite tools
PHASE 3
- Update core library for current processors/OS
- Integration with PerfDMF completed
- Joint TAU/PerfSuite automatic analysis tools completed
PSC
PHASE 1
- Install current project perrformance toolset at PSC
- Train consultants in the tools' new, advanced analysis modes
- Assess performance improvement opportunities of NEMO3D, ENZO, and NAMD groups
- Coordinate AG Performance Engineering seminars: Best Practices
PHASE 2
- Support performance engineering by NEMO3D, ENZO, NAMD, Cactus groups
- Apply updated tool features, tracking performance gains
- Coordinate AG Performance Engineering seminars: Tools for multicore
PHASE 3
- Inject performance engineering into additional applications
- Apply updated tool features, tracking performance gains
- Coordinate AG Performance Engineering seminars: Advanced Tools